CMOS Electronics : How It Works, How It Fails

Cover Contents 1 Electrical Circuit Analysis 1.1 Introduction 1.2 Voltage and Current Laws 1.2.1 Kirchhoff’s Voltage Law (KVL) 1.2.2 Kirchhoff’s Current Law (KCL) 1.3 Capacitors 1.3.1 Capacitor Connections 1.3.2 Capacitor Voltage Dividers 1.3.3 Charging and Discharging Capacitors 1.4 Diodes 1.4.1 Diode Resistor Circuits 1.4.2 Diode Resistance 1.5 Summary Bibliography Exercises 2 Semiconductor Physics 2.1 Semiconductor Fundamentals 2.1.1 Metals, Insulators, and Semiconductors 2.1.2 Carriers in Semiconductors: Electrons and Holes 2.1.3 Determining Carrier Population 2.2 Intrinsic and Extrinsic Semiconductors 2.2.1 n-Type Semiconductors 2.2.2 p-Type Semiconductors 2.3 Carrier Transport in Semiconductors 2.3.1 Drift Current 2.3.2 Diffusion Current 2.4 The pn Junction 2.5 Biasing the pn Junction: I–V Characteristics 2.5.1 The pn Junction under Forward Bias 2.5.2 The pn Junction under Reverse Bias 2.6 Parasitics in the Diode 2.7 Summary Bibliography Exercises 3 MOSFET Transistors 3.1 Principles of Operation: Long-Channel Transistors 3.1.1 The MOSFET as a Digital Switch 3.1.2 Physical Structure of MOSFETs 3.1.3 Understanding MOS Transistor Operation: A Descriptive Approach 3.1.4 MOSFET Input Characteristics 3.1.5 nMOS Transistor Output Characteristics 3.1.6 pMOS Transistor Output Characteristics 3.2 Threshold Voltage in MOS Transistors 3.3 Parasitic Capacitors in MOS Transistors 3.3.1 Non-Voltage-Dependent Internal Capacitors 3.3.2 Voltage-Dependent Internal Capacitors 3.4 Device Scaling: Short-Channel MOS Transistors 3.4.1 Channel Length Modulation 3.4.2 Velocity Saturation 3.4.3 Putting it All Together: A Physically Based Model 3.4.4 An Empirical Short-Channel Model for Manual Calculations 3.4.5 Other Submicron Effects 3.5 Summary Excercises 4 CMOS Basic Gates 4.1 Introduction 4.2 The CMOS Inverter 4.2.1 Inverter Static Operation 4.2.2 Dynamic Operation 4.2.3 Inverter Speed Property 4.2.4 CMOS Inverter Power Consumption 4.2.5 Sizing and Inverter Buffers 4.3 NAND Gates 4.4 NOR Gates 4.5 CMOS Transmission Gates 4.6 Summary Bibliography Exercises 5 CMOS Basic Circuits 5.1 Combinational logic 5.1.1 CMOS Static Logic 5.1.2 Tri-State Gates 5.1.3 Pass Transistor Logic 5.1.4 Dynamic CMOS Logic 5.2 Sequential Logic 5.2.1 Register Design 5.2.2 Semiconductor Memories (RAMs) 5.3 Input–Output (I/O) Circuitry 5.3.1 Input Circuitry: Protecting ICs from Outside Environment 5.3.2 Input Circuitry: Providing “Clean” Input Levels 5.3.3 Output Circuitry, Driving Large Loads 5.3.4 Input–Output Circuitry: Providing Bidirectional Pins 5.4 Summary References Exercises 6 Failure Mechanisms in CMOS IC Materials 6.1 Introduction 6.2 Materials Science of IC Metals 6.3 Metal Failure Modes 6.3.1 Electromigration 6.3.2 Metal Stress Voiding 6.3.3 Copper Interconnect Reliability 6.4 Oxide Failure Modes 6.4.1 Oxide Wearout 6.4.2 Hot-Carrier Injection (HCI) 6.4.3 Defect-Induced Oxide Breakdown 6.4.4 Process-Induced Oxide Damage 6.4.5 Negative Bias Temperature Instability (NBTI) 6.5 Conclusion Acknowledgments Bibliography Exercises 7 Bridging Defects 7.1 Introduction 7.2 Bridges in ICs: Critical Resistance and Modeling 7.2.1 Critical Resistance 7.2.2 Fault models for Bridging Defects on Logic Gate Nodes (BF) 7.3 Gate Oxide Shorts (GOS) 7.3.1 Gate Oxide Short Models 7.4 Bridges in Combinational Circuits 7.4.1 Nonfeedback Bridging Faults 7.4.2 Feedback Bridging Faults 7.5 Bridges in Sequential Circuits 7.5.1 Bridges in Flip-Flops 7.5.2 Semiconductor Memories 7.6 Bridging Faults and Technology Scaling 7.7 Conclusion References Exercises 8 Open Defects 8.1 Introduction 8.2 Modeling Floating Nodes in ICs 8.2.1 Supply–Ground Capacitor Coupling in Open Circuits 8.2.2 Effect of Surrounding Lines 8.2.3 Influence of the Charge from MOSFETs 8.2.4 Tunneling Effects 8.2.5 Other Effects 8.3 Open Defect Classes 8.3.1 Transistor-On Open Defect 8.3.2 Transistor Pair-On and Transistor Pair-On / Off 8.3.3 The Open Delay Defect 8.3.4 CMOS Memory Open Defect 8.3.5 Sequential Circuit Opens 8.4 Summary References Exercises 9 Parametric Failures 9.1 Introduction 9.2 Intrinsic Parametric Failures 9.2.1 Transistor Parameter Variation 9.2.2 Impact on Device Intrinsic Electrical Properties 9.2.3 Line Interconnect Intrinsic Parameter Variation 9.2.4 Temperature Effect 9.3 Intrinsic Parametric Failure Impact on IC Behavior 9.3.1 Interconnect Models 9.3.2 Noise 9.3.3 Delay 9.4 Extrinsic Parametric Failure 9.4.1 Extrinsic Weak Interconnect Opens 9.4.2 Extrinsic Resistive Vias and Contacts 9.4.3 Extrinsic Metal Mousebites 9.4.4 Extrinsic Metal Slivers 9.5 Conclusion References Exercises 10 Defect-Based Testing 10.1 Introduction 10.2 Digital IC Testing: The Basics 10.2.1 Voltage-Based Testing 10.2.2 Speed Testing 10.2.3 Current-Based Testing 10.2.4 Comparative Test Methods Studies 10.3 Design for Test 10.3.1 Scan Design 10.3.2 BIST 10.3.3 Special Test Structures for Next Levels of Assembly 10.4 Defect-Based Testing (DBT) 10.4.1 Bridge Defects 10.4.2 Opens 10.4.3 DBT Summary 10.5 Testing Nanometer ICs 10.5.1 Nanometer Effects on Testing 10.5.2 Voltage-Based Testing 10.5.3 Current-Based Testing 10.5.4 Delay Testing Using Statisitical Timing Analysis 10.5.5 Low-V DD Testing 10.5.6 Multiparameter Testing 10.6 Conclusions Bibliography References Exercises Appendix A: Solutions to Self-Exercises Index